FPGA 设计的 VHDL/4 位乘法器

FPGA 设计的 VHDL

4×4 位乘法器 VHDL 代码设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity Multiplier_VHDL is
   port
   (
      Nibble1, Nibble2: in std_logic_vector(1 downto 0);

      Result: out std_logic_vector(2 downto 0)
   );
end Multiplier_VHDL;

architecture Behavioral of Multiplier_VHDL is
begin

   Result <= std_logic_vector(unsigned(Nibble1) * unsigned(Nibble2));

end Behavioral;

仿真波形