FPGA 设计 VHDL/解码器

解码器 VHDL 代码

 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
 
entity Decoder is
   port(E : in std_logic;
        din : in std_logic_vector(2 downto 0);
        dout : out std_logic_vector(7 downto 0));
end Decoder;
 
architecture descript of Decoder is
begin
   
   dout <="00000000" when E='0' else
        "00000001" when E='1' and din="000" else
        "00000010" when E='1' and din="001" else
        "00000100" when E='1' and din="010" else
        "00001000" when E='1' and din="011" else
        "00010000" when E='1' and din="100" else
        "00100000" when E='1' and din="101" else
        "01000000" when E='1' and din="110" else
        "10000000" when E='1' and din="111";

end descript;

解码器测试平台文件

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
 
ENTITY tb_Decoder IS
END tb_Decoder;
 
ARCHITECTURE behavior OF tb_Decoder IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Decoder
    PORT(
         E : IN  std_logic;
         din : IN  std_logic_vector(2 downto 0);
         dout : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal E : std_logic := '0';
   signal din : std_logic_vector(2 downto 0) := (others => '0');

 	--Outputs
   signal dout : std_logic_vector(7 downto 0);
   -- No clocks detected in port list. Replace clk below with 
   -- appropriate port name 
 
	signal clk : std_logic;
	constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Decoder PORT MAP (
          E => E,
          din => din,
          dout => dout
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 
	
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		din <= "001";
		wait for clk_period;
		din <= "010";
		wait for clk_period;
		din <= "011";
		wait for clk_period;
		din <= "100";
		wait for clk_period;
		din <= "101";
		wait for clk_period;
		din <= "110";
		wait for clk_period;
		din <= "111";
		wait for clk_period;
		E <= '1';
		wait for clk_period;		
		din <= "000";
		wait for clk_period;
		din <= "001";
		wait for clk_period;
		din <= "010";
		wait for clk_period;
		din <= "011";
		wait for clk_period;
		din <= "100";
		wait for clk_period;
		din <= "101";
		wait for clk_period;
		din <= "110";
		wait for clk_period;
		din <= "111";
		
      -- insert stimulus here 

      wait;
   end process;

END;

解码器仿真波形

指向 ISE 导航到 RTL 图形的视频链接

在 Xilinx ISE 项目导航器中如何获取解码器 RTL 图形（电路图）的视频

另请参阅

• 编码器-解码器